; ; HD64180 Port Address Library ; Z8S180 Port updates ; ; Asynchronous Serial Communication Interface (ASCI) ; cntla0 equ 0 ; ASCI Control Register A Channel 0 cntla1 equ 1 ; ASCI Control Register A Channel 1 cntlb0 equ 2 ; ASCI Control Register B Channel 0 cntlb1 equ 3 ; ASCI Control Register B Channel 1 stat0 equ 4 ; ASCI Status Register Channel 0 stat1 equ 5 ; ASCI Status Register Channel 1 tdr0 equ 6 ; ASCI Transmit Data Register Channel 0 tdr1 equ 7 ; ASCI Transmit Data Register Channel 1 rdr0 equ 8 ; ASCI Receive Data Register Channel 0 rdr1 equ 9 ; ASCI Receive Data Register Channel 1 ; ; ; Clocked Serial Input/Output Port (CSI/O) ; cntr equ 0Ah ; CSI/O Control Register trdr equ 0Bh ; CSI/O Transmit/Receive Data Register ; ; ; Programmable Reload Timer (PRT) ; tmdr0l equ 0Ch ; PRT Timer Data Register Channel 0 Low tmdr0h equ 0Dh ; PRT Timer Data Register Channel 0 High rldr0l equ 0Eh ; PRT Timer Reload Register Channel 0 Low rldr0h equ 0Fh ; PRT Timer Reload Register Channel 0 High tcr equ 10h ; PRT Timer Control Register ; ; New ZS8180 Registers ; asext0 equ 12h ; ASCI0 Extension Control Register asext1 equ 13h ; ASCI1 Extension Control Register ; ; PRT continued (Z80180) ; tmdr1l equ 14h ; PRT Timer Data Register Channel 1 Low tmdr1h equ 15h ; PRT Timer Data Register Channel 1 High rldr1l equ 16h ; PRT Timer Reload Register Channel 1 Low rldr1h equ 17h ; PRT Timer Reload Register Channel 1 High ; ; New Z8S180 Registers ; astc0l equ 1Ah ; ASCI0 Time Contstant Low Register astc0h equ 1Bh ; ASCI0 Time Contstant High Register astc1l equ 1Ch ; ASCI1 Time Contstant Low Register astc1h equ 1Dh ; ASCI1 Time Contstant High Register clkmult equ 1Eh ; Clock Multiplier Register ccr equ 1Fh ; CPU Control Register ; ; DMA Controller (DMAC) ; sar0l equ 20h ; DMAC Source Address Register Channel 0 Low sar0h equ 21h ; DMAC Source Address Register Channel 0 High sar0b equ 22h ; DMAC Source Address Register Channel 0 Bank dar0l equ 23h ; DMAC Destination Address Register Channel 0 Low dar0h equ 24h ; DMAC Destination Address Register Channel 0 High dar0b equ 25h ; DMAC Destination Address Register Channel 0 Bank bcr0l equ 26h ; DMAC Byte Count Register Channel 0 Low bcr0h equ 27h ; DMAC Byte Count Register Channel 0 High mar1l equ 28h ; DMAC Memory Address Register Channel 1 Low mar1h equ 29h ; DMAC Memory Address Register Channel 1 High mar1b equ 2Ah ; DMAC Memory Address Register Channel 1 Bank iar1l equ 2Bh ; DMAC I/O Address Register Channel 1 Low iar1h equ 2Ch ; DMAC I/O Address Register Channel 1 High iar1b equ 2Dh ; DMAC I/O Address Register Channel 1 B (Z8S180) bcr1l equ 2Eh ; DMAC Byte Count Register Channel 1 Low bcr1h equ 2Fh ; DMAC Byte Count Register Channel 1 High dstat equ 30h ; DMAC Status Register dmode equ 31h ; DMAC Mode Register dcntl equ 32h ; DMAC Control Register ; ; ; Interrupt Control Registers ; il equ 33h ; INTERRUPT Vector Low Register itc equ 34h ; INT/TRAP Control Register ; ; ; Refresh Control Register ; rcr equ 36h ; REFRESH Control Register ; ; ; Memory Management Unit (MMU) ; cbr equ 38h ; MMU Common Base Register bbr equ 39h ; MMU Bank Base Register cbar equ 3Ah ; MMU Common/Bank Area Register ; ; ; I/O Control Register ; icr equ 3Fh ; I/O Control Register ; ; End of PORTS.LIB